Microprocessors and other digital systems commonly use synchronous pipelining techniques to increase throughput. These systems are functionally divided into synchronous pipeline stages that generally include an input register followed by a function section with an output section. Each pipeline stage receives its input from an upstream pipeline stage, and after completing its task, makes its output available to a downstream pipeline stage.
Synchronous pipeline systems commonly pre-charge lines activated by n-channel transistors HI and lines activated by p-channel transistors LO, thereby taking into account the respective speeds at which these transistor-types propagate HI/LO data values. In such pre-charged systems, each clock cycle can be divided into active (or evaluation) and pre-charge phases.
The specific problem to which the invention can be applied is increasing register throughput in pre-charged synchronous pipeline systems. A more general problem is reducing the effect of the required pre-charge phase on the throughput of a given pipeline stage.
For each pipeline stage, valid data must be available at its input register for at least the minimum set up time prior to the start of a clock cycle, allowing the master section of the input register to latch the valid data and initiate an active phase. Execution time--including active phase and pre-charge phase--varies, and the system clock is adjusted to accommodate the slowest stage.
Some pipeline stages include a combination of pre-charged and non-pre-charged logic. For example, a random access memory will generally include: (a) input address/data registers, (b) a memory section that includes a decoder front-end and a memory cell array defined by wordlines and bitlines, and (c) an output section that includes sense amps and drivers. While pre-charge operations are performed in connection with the memory array (wordlines and bitlines) and the sense amp, implementing pre-charge for the decoder front-end is generally impractical.
In normal operation of the memory stage, a valid address/data from an upstream stage may be available at the input address/data registers significantly prior to the beginning of a new clock cycle, i.e., while the memory stage is still in the pre-charge phase of the current clock cycle. This address/data is held at the input registers until the beginning of the new clock cycle, and the completion of the pre-charge phase, at which time it is latched by the master latch in the input register, and propagates through the slave latch to the decoder front-end, and thence to the pre-charged memory array. In other words, the memory stage awaits the completion of the pre-charge phase even though the valid address/data is available at the input registers.
Accordingly, a need exists for increasing throughput through pre-charged digital systems in general, and in particular, for reducing the effect of pre-charge on throughput.